The present invention relates to a method for forming high precision integrated circuit capacitors using polysilicon and titanium nitride electrodes.
High precision analog integrated circuits often require integrated circuit capacitors. Analog-to-digital and digital-to-analog converters require a number of precision capacitors for proper operation. For example in a true eighteen bit converter some of the capacitor requirements are a ratio stability of less than 0.00075% over 10 years, a voltage coefficient of less than 10 ppm/V, a temperature drift match of less than 0.05%/xc2x0 C. dielectric absorption of less than 0.00075%, capacitance greater than 0.5 fF/xcexcm2.
A crucial limitation in manufacturing high precision integrated circuit capacitors is the formation of the capacitor plates. Integrated circuit capacitors are formed by placing a thin dielectric layer between two conductive plates. In most instances the dielectric layer will comprise silicon oxide and the conductive plates can be formed using any conductive material present in the integrated circuit such as doped polycrystalline silicon and/or metals. In manufacturing the capacitor the conductive plates are formed by etching a conductive layer to the desired shape. Current etch techniques limit the precision of the capacitors so formed by producing nonlinear etch profiles, by leaving filaments of the material being etched, by trenching the surface of the integrated circuit, and by damaging the capacitor dielectric layer at the edge of the capacitor. There is therefore a need for a method to form high precision integrated circuit capacitors that is not limited by present etching constraints.
The instant invention describes a method for forming an integrated circuit capacitor. The method comprises forming a dielectric region in a semiconductor substrate and forming a patterned polysilicon layer on the dielectric region. An optional metal silicide layer can be formed on the polysilicon layer and a second dielectric layer formed over the polysilicon layer or metal silicide layer if one was formed. A conductive layer is formed over the dielectric layer and a hardmask layer is formed over the conductive layer.
In forming the capacitor structure the hardmask layer is etched and the conductive layer partially etched using a tow step dry etch process and the remaining conductive layer is etched using a wet etch process. In an embodiment of the method the first plasma etch step is a plasma etch process comprising Cl2, Ar, and BCl 3 and the second plasma etch step is a plasma etch process comprising Cl2, Ar, BCl3, and N2. The wet etch process is a two-step process where the first wet etch step comprises spraying a Piranha solution and a SC1 solution and the second wet etch step comprises a SC1 megasonic process.
In a further embodiment of the invention a three-step dry plasma etch process is used to etch all the layers to form the capacitor.